HD64F7144FW50V Datasheet, PDF (143/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

6. Interrupt Controller (INTC)
Interrupt acceptance
1
3
5 + m1 + m2 + m3
3
m1 m2 1 m3 1
IRQ
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
Interrupt service routine
start instruction
F DE E MMEME E
F
FDE
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed according to the results
of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Example of Pipeline Operation when IRQ Interrupt Is Accepted
Rev.4.00 Mar. 27, 2008 Page 97 of 882
REJ09B0108-0400