HD64F7144FW50V Datasheet, PDF (469/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

13. Serial Communication Interface (SCI)
Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3)
Logical Bit
Rate (bit/s)
250
500
1000
2500
5000
10000
25000
50000
100000
250000
500000
1000000
2500000
5000000
24
n
N
3
187
3
93
2
187
2
74
1
149
1
74
1
29
1
14
0
59
0
23
0
11
0
5
——
——
Operating Frequency Pφ (MHz)
25
26
28
n
N
n
N
n
N
3
194
3
202
3
218
3
97
3
101
3
108
2
194
2
202
2
218
2
77
2
80
2
86
1
155
1
162
1
174
1
77
1
80
1
86
0
249
——
1
34
0
124
0
129
0
139
0
62
0
64
0
69
0
24
0
25
0
27
——
0
12
0
13
——
——
0
6
——
——
——
——
——
——
30
n
N
3
233
3
116
2
233
2
93
1
187
1
93
——
0
149
0
74
0
29
0
14
——
0
2
——
Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4)
Operating Frequency Pφ (MHz)
Logical Bit
32
Rate (bit/s) n
N
34
n
N
36
n
N
38
n
N
250
3
249
——
——
——
500
3
124
3
132
3
140
3
147
1000
2
249
3
65
3
69
3
73
2500
2
99
2
105
2
112
2
118
5000
2
49
1
212
1
224
1
237
10000
2
24
1
105
1
112
1
118
25000
2
9
——
1
44
——
50000
2
4
0
169
0
179
0
189
100000
1
9
0
84
0
89
0
94
250000
1
3
0
33
0
35
0
37
500000
1
1
0
16
0
17
0
18
1000000
1
0
——
0
8
——
2500000
——
——
——
——
5000000
——
——
——
——
[Legend]
— : Can be set, but there will be a degree of error.
* : Continuous transfer is not possible.
40
n
N
——
3
155
3
77
2
124
1
249
1
124
1
49
1
24
0
99
0
39
0
19
0
9
0
3
0
1
Rev.4.00 Mar. 27, 2008 Page 423 of 882
REJ09B0108-0400