HD64F7144FW50V Datasheet, PDF (114/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

5. Exception Processing
5.3.2 Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends, the current
instruction finishes, and then address error exception processing starts. The CPU operates as
follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The start address of the exception service routine is fetched from the exception processing
vector table that corresponds to the occurred address error, and the program starts executing
from that address. The jump in this case is not a delayed branch.
Rev.4.00 Mar. 27, 2008 Page 68 of 882
REJ09B0108-0400