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HD64F7144FW50V Datasheet, PDF (159/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 | |||
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8. Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 8.1 shows a block diagram of the DTC.
The DTCâs register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR must be set to 1.
8.1 Features
⢠Transfer possible over any number of channels
⢠Three transfer modes
Normal, repeat, and block transfer modes available
⢠One activation source can trigger a number of data transfers (chain transfer)
⢠Direct specification of 32-bit address space possible
⢠Activation by software is possible
⢠Transfer can be set in byte, word, or longword units
⢠The interrupt that activated the DTC can be requested to the CPU
⢠Module standby mode can be set
DTCSH21A_010020020700
Rev.4.00 Mar. 27, 2008 Page 113 of 882
REJ09B0108-0400
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