HD64F7144FW50V Datasheet, PDF (459/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
3
PER
0
R/(W)* Parity Error
Indicates that a parity error occurred during reception
using parity addition in asynchronous mode, causing
abnormal termination.
[Setting condition]
• When a parity error is detected during reception
If a parity error occurs, the receive data is transferred to
RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the PER flag
is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its previous
state even if the RE bit in SCR is cleared to 0.
Rev.4.00 Mar. 27, 2008 Page 413 of 882
REJ09B0108-0400