HD64F7144FW50V Datasheet, PDF (415/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

11. Multi-Function Timer Pulse Unit (MTU)
The POE has input-level detection circuitry and output-level detection circuitry, as shown in the
block diagram of figure 11.114.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Output level
detection circuit
Output level
detection circuit
Output level
detection circuit
OCSR
ICSR1
POE3
POE2
POE1
POE0
Input level detection circuit
Falling-edge
detection circuit
Low-level
detection circuit
High-
impedance
request control
signal
Interrupt request
φ/8
φ/16
φ/128
[Legend]
OCSR: Output level control/status register
ICSR1: Input level control/status register
Figure 11.114 POE Block Diagram
Rev.4.00 Mar. 27, 2008 Page 369 of 882
REJ09B0108-0400