HD64F7144FW50V Datasheet, PDF (593/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

15. A/D Converter
15.3.3 A/D Control Register_0, 1 (ADCR_0, ADCR_1)
ADCR for each module controls A/D conversion started by an external trigger signal and selects
the operating clock.
Bit Bit Name Initial Value R/W Description
7 TRGE
0
R/W Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG or an MTU trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
6 CKS1
0
R/W Clock Select 1, 0
5 CKS0
0
R/W Select the A/D conversion time.
00: Pφ/32
01: Pφ/16
10: Pφ/8
11: Pφ/4
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
CKS[1,0] = b'11 can be set while Pφ ≤ 25 MHz.
4 ADST
0
R/W A/D Start
Starts or stops A/D conversion. When this bit is set to
1, A/D conversion is started. When this bit is cleared
to 0, A/D conversion is stopped and the A/D
converter enters the idle state. In single or single-
cycle scan mode, this bit is automatically cleared to 0
when A/D conversion ends on the selected single
channel. In continuous scan mode, A/D conversion is
continuously performed for the selected channels in
sequence until this bit is cleared by a software, reset,
or in software standby mode, or module standby
mode.
3 ADCS
0
R/W A/D Continuous Scan
Selects either single-cycle scan or continuous scan in
scan mode. This bit is valid only when scan mode is
selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
Rev.4.00 Mar. 27, 2008 Page 547 of 882
REJ09B0108-0400