HD64F7144FW50V Datasheet, PDF (474/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

13. Serial Communication Interface (SCI)
13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock as shown in figure 13.3. Thus the reception margin in asynchronous mode is given by
formula (1) below.
M = 0.5 – ¹ – ^{(D – 0.5)} – (L – 0.5) F × 100% ............................ Formula (1)
2N
N
Where
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Start bit
D0
D1
Data sampling
timing
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode
Rev.4.00 Mar. 27, 2008 Page 428 of 882
REJ09B0108-0400