HD64F7144FW50V Datasheet, PDF (528/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

14. I²C Bus Interface (IIC) Option
When the DTC is used, the IRIC flag is cleared automatically and transfer can be performed
continuously without CPU intervention. When the interface is in the I²C bus format and an
interrupt is generated so that IRIC becomes 1, other flags must be checked to locate the cause of
the IRIC bit becoming 1. Each possible cause has a corresponding flag. Precautions must be taken
when the data transfer has been completed.
When the ICDRE or ICDRF flag is set, the IRTR flag may be set, but in some cases it will not be.
In the I²C bus format in the slave mode, the IRTR flag, which is the DTC-activation request flag,
is not set during the period between the completion of data transfer after a slave-address (SVA)
match or a general call address match and the detection of the stop condition or transmission of the
next start condition. Even when the IRIC or IRTR flag has been set, the ICDRE or ICDRF flag
may not be set in some cases. When a continuous transfer is performed using the DTC, the IRIC or
IRTR flag is not cleared when the specified number of transfers is completed. On the other hand,
since the specified number of read/write operations has been completed, the ICDRE or the ICDRF
flag will already have been cleared.
The relationship between the flags and the various states of transfer is shown in table 14.4 and
table 14.5.
Rev.4.00 Mar. 27, 2008 Page 482 of 882
REJ09B0108-0400