SH7125 Datasheet, PDF (84/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 4 Clock Pulse Generator (CPG)
4.4.2 Oscillation Stop Detection Control Register (OSCCR)
OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects
flag status output to an external pin. OSCCR can be accessed only in bytes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
OSC
STOP
-
OSC
ERS
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W
Bit
7 to 3
2
1
0
Bit Name

Initial
Value
All 0
OSCSTOP 0

0
OSCERS 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
Oscillation Stop Detection Flag
[Setting conditions]
• When a stop in the clock input is detected during
normal operation
• When software standby mode is entered
[Clearing conditions]
• By a power-on reset input through the RES pin
• When software standby mode is canceled
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Oscillation Stop Detection Flag Output Select
Selects whether to output the oscillation stop detection
flag signal through the WDTOVF pin.
0: Outputs only the WDT overflow signal through the
WDTOVF pin
1: Outputs the WDT overflow signal and the oscillation
stop detection flag signal through the WDTOVF pin
Rev. 3.00 Sep. 27, 2007 Page 64 of 758
REJ09B0243-0300