SH7125 Datasheet, PDF (17/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 14 Compare Match Timer (CMT) ........................................................501
14.1 Features.............................................................................................................................. 501
14.2 Register Descriptions ......................................................................................................... 502
14.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 503
14.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 503
14.2.3 Compare Match Counter (CMCNT) ..................................................................... 505
14.2.4 Compare Match Constant Register (CMCOR) ..................................................... 505
14.3 Operation ........................................................................................................................... 506
14.3.1 Interval Count Operation ...................................................................................... 506
14.3.2 CMCNT Count Timing......................................................................................... 506
14.4 Interrupts............................................................................................................................ 507
14.4.1 CMT Interrupt Sources ......................................................................................... 507
14.4.2 Timing of Setting Compare Match Flag ............................................................... 507
14.4.3 Timing of Clearing Compare Match Flag............................................................. 507
14.5 Usage Notes ....................................................................................................................... 508
14.5.1 Module Standby Mode Setting ............................................................................. 508
14.5.2 Conflict between Write and Compare-Match Processes of CMCNT ................... 508
14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 509
14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 510
14.5.5 Compare Match between CMCNT and CMCOR ................................................. 510
Section 15 Pin Function Controller (PFC).........................................................511
15.1 Register Descriptions ......................................................................................................... 519
15.1.1 Port A I/O Register L (PAIORL).......................................................................... 520
15.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4).................................. 520
15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH)........................................ 531
15.1.4 Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1) ... 532
15.1.5 Port E I/O Register L (PEIORL)........................................................................... 537
15.1.6 Port E Control Registers L1 to L4 (PECRL1 to PECRL4) ................................... 537
15.1.7 IRQOUT Function Control Register (IFCR) ........................................................ 547
15.2 Usage Notes ....................................................................................................................... 548
Section 16 I/O Ports...........................................................................................549
16.1 Port A................................................................................................................................. 550
16.1.1 Register Descriptions............................................................................................ 551
16.1.2 Port A Data Register L (PADRL) ......................................................................... 551
16.1.3 Port A Port Register L (PAPRL) .......................................................................... 555
16.2 Port B ................................................................................................................................. 557
16.2.1 Register Descriptions............................................................................................ 557
16.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ........................................ 558
Rev. 3.00 Sep. 27, 2007 Page xvii of xx