SH7125 Datasheet, PDF (365/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.7.17 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 9.122 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
MPφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
TCFV
H'FFFF
Disabled
H'0000
Figure 9.122 Contention between Overflow and Counter Clearing
Rev. 3.00 Sep. 27, 2007 Page 345 of 758
REJ09B0243-0300