SH7125 Datasheet, PDF (104/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 5 Exception Handling
5.7 Stack States after Exception Handling Ends
The stack states after exception handling ends are shown in table 5.11.
Table 5.11 Stack Status after Exception Handling Ends
Types
Stack State
Address error (when the instruction
that caused an exception is placed in
the delay slot)
SP →
Address of
delayed branch instruction
32 bits
SR
32 bits
Address error (other than above)
SP →
Address of instruction that
caused exception
SR
32 bits
32 bits
Interrupt
SP →
Address of instruction
after executed instruction
SR
32 bits
32 bits
Trap instruction
SP →
Address of instruction
after TRAPA instruction
SR
32 bits
32 bits
Rev. 3.00 Sep. 27, 2007 Page 84 of 758
REJ09B0243-0300