SH7125 Datasheet, PDF (761/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
Figure 8.3 Timing of Read Access 150
to the Peripheral Bus
(Iclk:Bclk:Pclk = 4:2:1)
Added
Iclk
L bus
Bclk
I bus
Pclk
Peripheral bus
Table 9.28 TIORU_5, TIORV_5, 187 Amended
and TIORW_5 (Channel 5)
Description
Bit 4
IOC4
TGRU_5, TGRV_5, and TIC5U, TIC5V, and TIC5W Pin
TGRW_5 Function
Function
Input capture register _{Capture at trough in}
1
complementary PWM mode
Capture at trough in
complementary PWM mode
Capture at trough in
complementary PWM mode
Capture at trough in
complementary PWM mode
Capture at trough in
complementary PWM mode
Capture at trough in
complementary PWM mode
Rev. 3.00 Sep. 27, 2007 Page 741 of 758
REJ09B0243-0300