SH7125 Datasheet, PDF (338/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3
and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in
channel 0 are not set by the occurrence of an input capture.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one
each for channels 1 and 2.
Rev. 3.00 Sep. 27, 2007 Page 318 of 758
REJ09B0243-0300