SH7125 Datasheet, PDF (757/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Main Revisions and Additions in this Edition
Item
–
Table 1.1 Features
Page Revision (See Manual for Details)
–
Added
VQFN-64 and VQFN-52 specifications
Descriptions of on-chip 32-kbyte flash memory for
SH7124
4
Deleted
Items
Specification
Multi-function _•
timer pulse unit 2
(MTU2)
Pulse output modes
One shot, toggle, PWM,
complementary PWM, and
reset-synchronized PWM
modes
Table 2.12 Arithmetic Operation 40
Instructions
Amended
Instruction
SUBV Rm,Rn
T Bit
Underflow
4.1 Features
55
Table 4.4 Frequency Division
60
Ratios Specifiable with FRQCR
Deleted
• Five clocks generated independently
An internal clock (If) for the CPU and cache; a
peripheral clock (Pf) for the on-chip peripheral modules;
a bus clock (Bf = CK) for the external bus interface; and
a MTU2 clock (MPf) for the on-chip MTU2 module.
Deleted
Notes: 2. The output frequency of the PLL circuit is the
product of the frequency of the input from the
crystal resonator or EXTAL pin and the
multiplication ratio (×8) of the PLL circuit. This
output frequency must be 50 MHz or lower.
Rev. 3.00 Sep. 27, 2007 Page 737 of 758
REJ09B0243-0300