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SH7125 Datasheet, PDF (60/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer | |||
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Section 2 CPU
Instruction
Operation
Code
Execution
Cycles
DMULU.L Rm,Rn
Unsigned operation of
Rn à Rm â MACH,
MACL 32 Ã 32 â 64 bits
0011nnnnmmmm0101 2 to 5*
DT
Rn
Rn - 1 â Rn, if Rn = 0, 1 â 0100nnnn00010000 1
T, else 0 â T
EXTS.B Rm,Rn
A byte in Rm is sign-
extended â Rn
0110nnnnmmmm1110 1
EXTS.W Rm,Rn
A word in Rm is sign-
extended â Rn
0110nnnnmmmm1111 1
EXTU.B Rm,Rn
A byte in Rm is zero-
extended â Rn
0110nnnnmmmm1100 1
EXTU.W Rm,Rn
A word in Rm is zero-
extended â Rn
0110nnnnmmmm1101 1
MAC.L
@Rm+,@Rn+
Signed operation of (Rn)
à (Rm) + MAC â MAC,
32 Ã 32 + 64 â 64 bits
0000nnnnmmmm1111 2 to 5*
MAC.W
@Rm+,@Rn+
Signed operation of (Rn)
à (Rm) + MAC â MAC,
16 Ã 16 + 64 â 64 bits
0100nnnnmmmm1111 2 to 4*
MUL.L Rm,Rn
Rn à Rm â MACL
32 Ã 32 â 32 bits
0000nnnnmmmm0111 2 to 5*
MULS.W Rm,Rn
Signed operation of Rn
à Rm â MAC
16 Ã 16 â 32 bits
0010nnnnmmmm1111 1 to 3*
MULU.W Rm,Rn
Unsigned operation of
Rn à Rm â MAC
16 Ã 16 â 32 bits
0010nnnnmmmm1110 1 to 3*
NEG
Rm,Rn
0-Rm â Rn
0110nnnnmmmm1011 1
NEGC Rm,Rn
0-Rm-T â Rn,
Borrow â T
0110nnnnmmmm1010 1
SUB Rm,Rn
Rn-Rm â Rn
0011nnnnmmmm1000 1
SUBC Rm,Rn
Rn-RmâT â Rn,
Borrow â T
0011nnnnmmmm1010 1
SUBV Rm,Rn
Rn-Rm â Rn,
Underflow â T
0011nnnnmmmm1011 1
Note: * Indicates the number of execution cycles for normal operation.
T Bit
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Comparison
result
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Borrow
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Borrow
Underflow
Rev. 3.00 Sep. 27, 2007 Page 40 of 758
REJ09B0243-0300
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