SH7125 Datasheet, PDF (680/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 19 Power-Down Modes
Table 19.1 States of Power-Down Modes
State
Mode
CPU
On-Chip
Transition Method CPG CPU Register Memory
On-Chip
Peripheral
Modules Canceling Procedure
Sleep Execute SLEEP
Runs Halts Held
Runs
Run
• Reset
instruction with STBY
bit in STBCR1
cleared to 0.
Software
standby
Execute SLEEP
Halts
instruction with STBY
bit in STBCR1 and
STBYMD bit in
STBCR6 set to 1.
Halts
Held
Halts
Halt
(contents
retained)
• Interrupt by NMI or
IRQ
• Power-on reset by
the RES pin
Module
standby
Set MSTP bits in Runs Runs Held
STBCR2 to STBCR5
to 1.
Specified Specified
module halts module
(contents halts
retained)
• Clear MSTP bit to 0
• Power-on reset (for
modules whose
MSTP bit has an
initial value of 0)
Note: For details on the states of on-chip peripheral module registers in each mode, refer to
section 20.3, Register States in Each Operating Mode. For details on the pin states in each
mode, refer to appendix A, Pin States.
Rev. 3.00 Sep. 27, 2007 Page 660 of 758
REJ09B0243-0300