SH7125 Datasheet, PDF (272/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Cascaded Operation Example (c) in SH7125: Figure 9.23 illustrates the operation when
TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to
1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture
conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2
have selected both the rising and falling edges for the input capture timing. Under these
conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2
input capture conditions.
TCNT_2 value
H'FFFF
H'C256
H'9192
H'6128
H'2064
H'0000
TCNT_1
H'0512
H'0513
H'0514
Time
TIOC1A
TIOC2A
TGRA_1
H'0512
H'0513
H'0514
TGRA_2
H'6128
H'2064
H'C256
H'9192
Figure 9.23 Cascaded Operation Example (c)
Cascaded Operation Example (d) in SH7125: Figure 9.24 illustrates the operation when
TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include
the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits
in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input
capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for
the input capture timing.
Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture
occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture
condition although the I2AE bit in TICCR has been set to 1.
Rev. 3.00 Sep. 27, 2007 Page 252 of 758
REJ09B0243-0300