SH7125 Datasheet, PDF (157/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 7 User Break Controller (UBC)
7.3.4 Sequential Break
1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break
condition matches after a channel A break condition matches. A user break is not generated
even if a channel B break condition matches before a channel A break condition matches.
When channels A and B conditions match at the same time, the sequential break is not issued.
To clear the channel A condition match when a channel A condition match has occurred but a
channel B condition match has not yet occurred in a sequential break specification, clear the
SEQ bit in BRCR to 0 and clear also the condition match flag to 0 in channel A.
2. In sequential break specification, the L or I bus can be selected and the execution times break
condition can be also specified. For example, when the execution times break condition is
specified, the break condition is satisfied when a channel B condition matches with BETR =
H'0001 after a channel A condition has matched.
7.3.5 Value of Saved Program Counter
When a break occurs, the address of the instruction from where execution is to be resumed is
saved in the stack, and the exception handling state is entered. If the L bus is specified as a break
condition, the instruction at which the break should occur can be clearly determined (except for
when data is included in the break condition). If the I bus is specified as a break condition, the
instruction at which the break should occur cannot be clearly determined.
1. When instruction fetch (before instruction execution) is specified as a break condition:
The address of the instruction that matched the break condition is saved in the stack. The
instruction that matched the condition is not executed, and the break occurs before it. However
when a delay slot instruction matches the condition, the address of the delayed branch
instruction is saved in the stack.
2. When instruction fetch (after instruction execution) is specified as a break condition:
The address of the instruction following the instruction that matched the break condition is
saved in the stack. The instruction that matches the condition is executed, and the break occurs
before the next instruction is executed. However, when a delayed branch instruction or delay
slot matches the condition, these instructions are executed, and the branch destination address
is saved in the stack.
3. When data access (address only) is specified as a break condition:
The address of the instruction immediately after the instruction that matched the break
condition is saved in the stack. The instruction that matches the condition is executed, and the
break occurs before the next instruction is executed. However when a delay slot instruction
matches the condition, the branch destination address is saved in the stack.
Rev. 3.00 Sep. 27, 2007 Page 137 of 758
REJ09B0243-0300