SH7125 Datasheet, PDF (150/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
5
DBEB
0
R/W Data Break Enable B
Selects whether or not the data bus condition is
included in the break condition of channel B.
0: No data bus condition is included in the condition of
channel B
1: The data bus condition is included in the condition of
channel B
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
SEQ
0
R/W Sequence Condition Select
Selects two conditions of channels A and B as
independent or sequential conditions.
0: Channels A and B are compared under independent
conditions
1: Channels A and B are compared under sequential
conditions (channel A, then channel B)
2, 1

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
ETBE
0
R/W Number of Execution Times Break Enable
Enables the execution-times break condition only on
channel B. If this bit is 1 (break enable), a user break is
requested when the number of break conditions
matches with the number of execution times that is
specified by BETR.
0: The execution-times break condition is disabled on
channel B
1: The execution-times break condition is enabled on
channel B
Rev. 3.00 Sep. 27, 2007 Page 130 of 758
REJ09B0243-0300