SH7125 Datasheet, PDF (351/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. Figures 9.105 and 9.106 show the timing for status flag clearing by the CPU.
MPφ, Pφ
TSR write cycle
T1
T2
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 9.105 Timing for Status Flag Clearing by CPU (Channels 0 to 4)
MPφ, Pφ
TSR write cycle
T1
T2
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 9.106 Timing for Status Flag Clearing by CPU (Channel 5)
Rev. 3.00 Sep. 27, 2007 Page 331 of 758
REJ09B0243-0300