SH7125 Datasheet, PDF (758/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
4.4.1 Frequency Control Register 61
(FRQCR)
Added/Deleted
Before making changes to FRQCR, set the module stop
bit in the standby control register 2, 3, 4, 5, and 6 to 1
and stop clock supply to each module except the CPU,
on-chip ROM, and on-chip-RAM.
4.4.1 Frequency Control Register 62,
(FRQCR)
63
Added
Bit
Bit Name Description
14 to 12 IFC[2:0] Internal Clock (Iφ) Frequency Division Ratio
If a prohibited value is specified, subsequent
operation is not guaranteed.
11 to 9 BFC[2:0] Bus Clock (Bφ) Frequency Division Ratio
If a prohibited value is specified, subsequent
operation is not guaranteed.
8 to 6 PFC[2:0] Peripheral Clock (Pφ) Frequency Division Ratio
If a prohibited value is specified, subsequent
operation is not guaranteed.
2 to 0 MPFC[2:0] MTU2 Clock (MPφ) Frequency Division Ratio
If a prohibited value is specified, subsequent
operation is not guaranteed.
4.5 Changing Frequency
65 Added/Deleted
4. The clock frequencies are immediately changed to
the specified values after FRQCR setting is
completed. After an instruction to rewrite FRQCR
has been issued, the actual clock frequencies will
change after (1 to 24n) cyc + 11Bf + 7Pf.
n: Division ratio specified by the BFC bit in FRQCR
(1, 1/2, 1/4, or 1/8)
cyc: Clock obtained by dividing EXTAL by 8 with the
PLL.
Note: (1 to 24n) depends on the internal state.
Rev. 3.00 Sep. 27, 2007 Page 738 of 758
REJ09B0243-0300