SH7125 Datasheet, PDF (763/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Item
Figure 10.5 Pin State when a
Power-On Reset is Issued from
the Watchdog Timer
Page Revision (See Manual for Details)
400 Added
Pφ
POE input
Pin state
Timer output
PFC setting value
Timer output
High impedance state
Timer
output
1Pφ cycle
General input
General input
Power-on reset by WDT
Figure 11.3 Operation in
409
Watchdog Timer Mode (When
WTCNT Count Clock is Specified
to Pφ/32 by CKS2 to CKS0)
Added
Internal reset signal
(power-on reset selected)
Internal reset signal
(manual reset selected)
35 Pφ + one cycle of count clock
18 Pφ clock
12.3.2 Receive Data Register
(SCRDR)
415 Amended
Bit: 7
6
5
4
3
2
1
0
12.3.4 Transmit Data Register
(SCTDR)
Initial value: -
-
-
-
-
-
-
-
R/W: ^-
-
-
-
-
-
-
-
R
R
RR
R
R
R
R
416 Amended
Bit: 7
6
5
4
3
2
1
0
12.3.8 Serial Port Register
(SCSPTR)
428
Initial value: -
R/W: ^-
R/W
Amended
-
-
-
-
R/W R/W
-
-
R/W
-
-
R/W
-
-
R/W
-
-
-
-
R/W R/W
Bit: 7
6
5
4
3
2
1
0
EIO
-
-
-
SPB1IO
SPB1DT
SPB0IO
-
SPB0DT
Initial value: 0
0
0
0
0 Undefined 0 Undefined
R/W: R/W -
-
- R/W ^{0 R/W 1}
R/W ^-
W
Rev. 3.00 Sep. 27, 2007 Page 743 of 758
REJ09B0243-0300