SH7125 Datasheet, PDF (81/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 4 Clock Pulse Generator (CPG)
4.4 Register Descriptions
The CPG has the following registers.
For details on the addresses of these registers and the states of these registers in each processing
state, see section 20, List of Registers
Table 4.5 Register Configuration
Register Name
Frequency control register
Oscillation stop detection
control register
Abbrevia-
tion
R/W Initial Value Address
Access Size
FRQCR R/W H'36DB
H'FFFFE800 16
OSCCR R/W H'00
H'FFFFE814 8
4.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the
internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). FRQCR can be
accessed only in words.
FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT
overflow).
Before making changes to FRQCR, stop clock supply to each module except the CPU, on-chip
ROM, and on-chip-RAM.
Bit: 15
-
Initial value: 0
R/W: R
14 13 12
IFC[2:0]
0
1
1
R/W R/W R/W
11 10 9
BFC[2:0]
0
1
1
R/W R/W R/W
8
7
6
PFC[2:0]
0
1
1
R/W R/W R/W
5
-
0
R/W
4
-
1
R/W
3
-
1
R/W
2
1
0
MPFC[2:0]
0
1
1
R/W R/W R/W
Rev. 3.00 Sep. 27, 2007 Page 61 of 758
REJ09B0243-0300