SH7125 Datasheet, PDF (11/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

5.5.4 General Illegal Instructions..................................................................................... 82
5.6 Cases when Exceptions are Accepted .................................................................................. 83
5.7 Stack States after Exception Handling Ends........................................................................ 84
5.8 Usage Notes ......................................................................................................................... 86
5.8.1 Value of Stack Pointer (SP) .................................................................................... 86
5.8.2 Value of Vector Base Register (VBR) .................................................................... 86
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling.......... 86
5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 87
Section 6 Interrupt Controller (INTC) .................................................................89
6.1 Features................................................................................................................................ 89
6.2 Input/Output Pins................................................................................................................. 91
6.3 Register Descriptions ........................................................................................................... 92
6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 93
6.3.2 IRQ Control Register (IRQCR) .............................................................................. 94
6.3.3 IRQ Status register (IRQSR) .................................................................................. 96
6.3.4 Interrupt Priority Registers A to F and H to M
(IPRA to IPRF and IPRH to IPRM) ....................................................................... 99
6.4 Interrupt Sources................................................................................................................ 102
6.4.1 External Interrupts ................................................................................................ 102
6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 103
6.4.3 User Break Interrupt ............................................................................................. 103
6.5 Interrupt Exception Handling Vector Table....................................................................... 104
6.6 Interrupt Operation ............................................................................................................ 107
6.6.1 Interrupt Sequence ................................................................................................ 107
6.6.2 Stack after Interrupt Exception Handling ............................................................. 110
6.7 Interrupt Response Time.................................................................................................... 110
6.8 Usage Note......................................................................................................................... 112
Section 7 User Break Controller (UBC) ............................................................113
7.1 Features.............................................................................................................................. 113
7.2 Register Descriptions ......................................................................................................... 115
7.2.1 Break Address Register A (BARA) ...................................................................... 116
7.2.2 Break Address Mask Register A (BAMRA)......................................................... 116
7.2.3 Break Bus Cycle Register A (BBRA)................................................................... 117
7.2.4 Break Data Register A (BDRA) ........................................................................... 119
7.2.5 Break Data Mask Register A (BDMRA) .............................................................. 120
7.2.6 Break Address Register B (BARB) ...................................................................... 121
7.2.7 Break Address Mask Register B (BAMRB) ......................................................... 122
7.2.8 Break Data Register B (BDRB) ............................................................................ 123
Rev. 3.00 Sep. 27, 2007 Page xi of xx