SH7125 Datasheet, PDF (167/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
Section 8 Bus State Controller (BSC)
The bus state controller (BSC) controls data transmission and reception between the internal buses
(L bus, I bus, and peripheral bus) and also controls the CPU’s access to the on-chip FLASH, on-
chip RAM, and on-chip peripheral I/O.
8.1 Features
• On-chip FLASH and RAM interface
 32-bit data access per one clock cycle (I φ synchronous)
8.2 Address Map
The address map is listed in table 8.1.
Table 8.1 Address Map
Size
Address
128 Kbytes 64 Kbytes 32 Kbytes Bus
Type of Memory Version Version Version Width
H'00000000 to H'00007FFF On-chip FLASH 128 Kbytes 64 Kbytes 32 Kbytes 32
H'00008000 to H'0000FFFF
Reserved
H'00010000 to H'0001FFFF
Reserved
H'00020000 to H'83FFFFFF Reserved




H'84000000 to H'84007FFF On-chip FLASH 128 Kbytes 64 Kbytes 32 Kbytes 8
H'84008000 to H'8400FFFF ^{programming area}
Reserved
H'84010000 to H'8401FFFF
Reserved
H'84020000 to H'FFFF9FFF Reserved




H'FFFFA000 to H'FFFFBFFF On-chip RAM
8 Kbytes 8 Kbytes 8 Kbytes 32
H'FFFFC000 to H'FFFFFFFF On-chip peripheral 


8/16
I/O
8.3 Access to on-chip FLASH and on-chip RAM
Access to the on-chip FLASH for read is synchronized with I φ clock and is executed in one clock
cycle. For details on programming and erasing, see section 17, Flash Memory.
Rev. 3.00 Sep. 27, 2007 Page 147 of 758
REJ09B0243-0300