SH7125 Datasheet, PDF (291/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
TGRC_3 TCBR
TDDR TGRA_3 TCDR
Comparator
TCNT_3 TCNTS TCNT_4
Comparator
Match
signal
Match
signal
PWM cycle
output
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
External cutoff
input
POE0
POE1
POE3
TGRD_3
TGRC_4
TGRD_4
External cutoff
interrupt
: Registers that can always be read or written from the CPU
: Registers that can be read or written from the CPU
(but for which access disabling can be set by TRWER)
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
Figure 9.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
Rev. 3.00 Sep. 27, 2007 Page 271 of 758
REJ09B0243-0300