SH7125 Datasheet, PDF (169/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
Iclk
L bus
Bclk
I bus
Pclk
Peripheral bus
Figure 8.1 Timing of Write Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:1:1)
Figure 8.2 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk =
4:4:1. From the L bus, to which the CPU is connected, data is output in synchronization with Iclk.
When Iclk:Bclk = 1:1, a period of 3 Iclk + Bclk is required to transfer data from the L bus to the I
bus. In data transfer from the I bus to the peripheral bus, there are four BIclk cycles in a single
Pclk cycle when Bclk:Pclk = 4:1, and data can therefore be output onto the peripheral bus in four
possible timings within one Pclk cycle. Accordingly, a maximum of four Bclk cycles of period
(four Bclk cycles in the example shown in the figure) is required before the rising edge of Pclk, on
which data is transferred from the I bus to the peripheral bus. Because of this, data is transferred
from the I bus to the peripheral bus in a period of (1 + m) × Bclk (m = 0 to 3) when Bclk:Pclk =
4:1. The relation of the timing of data output to the I bus and the rising edge of Pclk depends on
the state of program execution. In the case shown in figure 8.2, where Iclk = Bclk = 1:1, the period
required for access by the CPU is 3 × Iclk + (1 + m) × Bclk + 2 × Pclk.
Iclk
L bus
Bclk
I bus
Pclk
Peripheral bus
Figure 8.2 Timing of Write Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:4:1)
Figure 8.3 shows an example of timing of read access to the peripheral bus when Iclk:Bclk:Pclk =
4:2:1. Transfer from the L bus to the peripheral bus is performed in the same way as for write
access. In the case of reading, however, values output onto the peripheral bus must be transferred
to the CPU. Transfers from the external bus to the I bus and from the I bus to the L bus are again
performed in synchronization with rising edges of the respective bus clocks. 2 × Iclk cycles of
Rev. 3.00 Sep. 27, 2007 Page 149 of 758
REJ09B0243-0300