SH7125 Datasheet, PDF (63/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 2 CPU
2.5.6 Branch Instructions
Table 2.15 Branch Instructions
Instruction
Operation
Code
Execution
Cycles
BF label
If T = 0, disp × 2 + PC →
PC;
if T = 1, nop
10001011dddddddd 3/1*
BF/S label
Delayed branch, if T = 0,
disp × 2 + PC → PC;
if T = 1, nop
10001111dddddddd 2/1*
BT label
If T = 1, disp × 2 + PC →
PC;
if T = 0, nop
10001001dddddddd 3/1*
BT/S label
Delayed branch, if T = 1,
disp × 2 + PC → PC;
if T = 0, nop
10001101dddddddd 2/1*
BRA label
Delayed branch,
disp × 2 + PC → PC
1010dddddddddddd 2
BRAF Rm
Delayed branch,
Rm + PC → PC
0000mmmm00100011 2
BSR label
Delayed branch, PC → PR, 1011dddddddddddd 2
disp × 2 + PC → PC
BSRF Rm
Delayed branch, PC → PR, 0000mmmm00000011 2
Rm + PC → PC
JMP @Rm
Delayed branch, Rm → PC 0100mmmm00101011 2
JSR @Rm
Delayed branch, PC → PR, 0100mmmm00001011 2
Rm → PC
RTS
Delayed branch, PR → PC 0000000000001011 2
Note: * One cycle when the branch is not executed.
T Bit
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Rev. 3.00 Sep. 27, 2007 Page 43 of 758
REJ09B0243-0300