SH7125 Datasheet, PDF (325/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) When rewriting a buffer register within a carrier cycle after TGIA_3 interrupt occurred.
TGIA_3 interrupt occurred
TGIA_3 interrupt occurred
TCNT_3
TCNT_4
Buffer register rewriting timing
Buffer transfer-enabled period
TITCR[6:4]
2
Buffer register rewriting timing
TITCNT[6:4]
0
1
2
0
1
Buffer register
Data
Data1
Data2
Temporary register
Data
Data1
Data2
Compare register
Data
Data1
(2) When rewriting a buffer register after a carrier cycle passed from occurring TGIA_3 interrupt.
TGIA_3 interrupt occurred
TGIA_3 interrupt occurred
Data2
TCNT_3
TCNT_4
Buffer register rewriting timing
Buffer transfer-enabled period
TITCR[6:4]
2
TITCNT[6:4]
0
1
2
0
1
Buffer register
Data
Data1
Temporary register
Data
Data1
Compare register
Data
Note: * Buffer transfer at the crest is selected.
The skipping count is set to two.
T3AEN is set to 1.
Data1
Figure 9.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping
(BTE1 = 1 and BTE0 = 0)
Rev. 3.00 Sep. 27, 2007 Page 305 of 758
REJ09B0243-0300