SH7125 Datasheet, PDF (409/782 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer

Section 10 Port Output Enable (POE)
Initial
Bit
Bit Name value R/W Description
14 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
OCE1
0
R/W*² Output Short High-Impedance Enable 1
This bit specifies whether to place the pins in high-
impedance state when the OSF1 bit in OCSR1 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
8
OIE1
0
R/W Output Short Interrupt Enable 1
This bit enables or disables interrupt requests when the
OSF1 bit in OCSR is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
10.3.3 Input Level Control/Status Register 3 (ICSR3)
ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the
enable/disable of interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
- POE8F -
- POE8E PIE3
-
-
-
-
-
-
POE8M[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/(W)*¹ R
R R/W*² R/W R
R
R
R
R
R R/W*² R/W*²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Rev. 3.00 Sep. 27, 2007 Page 389 of 758
REJ09B0243-0300