OXMPCI952 Datasheet, PDF (99/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Read from EPP Data Register (EPP Read Data cycle)
PCI CLK no (1^st Transaction)
1
- Start of PCI Read from EPP Data register
4
- Start of EPP data read cycle on parallel port side.
8
- PCI transaction completes with a ‘retry’ (without affecting ongoing EPP read data cycle) as EPP cycle cannot complete within 16 PCI CLK cycles
7-8
- Peripheral Asserts BUSY in response to the host driving AFD_N low.
11
- Host responds to BUSY by de-asserting AFD_N (3 clock cycles after sampling BUSY)
14-15 - Peripheral Deasserts BUSY
- EPP cycle completed.
PCI CLK no (Retry Transaction)
1
- Start of Retry transaction, to the original read from EPP data register
5
- Retry transaction completes with “Data Transfer”, without initiating another EPP read Data cycle.
Tafd (PCI clk to valid AFD_N)
- 22ns max*
Tstb (PCI clk to valid STB_N)
- 22ns max*
Tpd (PCI clk to valid Parallel Data) - 22ns max*
EPP Read Data Cycle duration is dependant upon the timing response of the peripheral’s BUSY line and the parallel port filters.
Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to
the peripheral’s BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
DS-0020 Jun 05
Page 99