OXMPCI952 Datasheet, PDF (27/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
5.3.2 PCI access to 8-bit local bus
When the local bus is enabled (mode = 0), access to the
bus works in a similar fashion to the internal UARTs. The
function reserves a block of I/O space and a block of
memory space. The I/O block size is user definable in the
range of 4 to 256 bytes, and the memory range is fixed at
4K bytes.
I/O space
In order to minimise the usage of IO space, the block size
for BAR0 of Function1 is user definable in the range of 4 to
256 bytes. Having assigned the address range, the user
can define two adjacent address bits to decode up to four
chip selects internally. This facility allows glueless
implementation of the local bus connecting to four external
peripheral chips. The address range and the lower address
bit for chip-select decoding (Lower-Address-CS-Decode)
are defined in the Local Bus Configuration register (see
LT2 [26:20] in section 5.4).
The 8-bit Local Bus has eight address lines (LBA[7:0]) that
correspond to the maximum I/O address space. If the
maximum allowable block size is allocated to the I/O space
(i.e. 256 bytes), then as access in I/O space is byte
aligned, LBA[7:0] equal PCI AD[7:0] respectively. When the
user selects an address range which is less than 256
bytes, the corresponding upper address lines will be set to
logic zero.
The region can be divided into four chip-select regions
when the user selects the second uppermost non-zero
address bit for chip-select decoding. For example if 32-
bytes of I/O space are reserved, the local bus address lines
A[4:0] are active and the remaining address lines are set to
zero. To generate four chip-selects the user should select
A3 as the Lower-Address-CS-Decode. In this case A[4:3]
will be used internally to decode chip-selects, asserting
LBCS0# when the address offset is 00-07h, LBCS1# when
the offset is 08-0Fh, LBCS2# when the offset is 10-17h,
and LBCS3# when the offset is 18-1Fh.
The region can be divided into two chip-select regions by
selecting the uppermost address bit to decode chip selects.
In the above example, the user can select A4 as the
Lower-Address-CS-Decode, thus using A[5:4] internally to
decode chip selects. As in this example LBA5 is always
zero, only chip-select lines LBCS0# and LBCS1# will be
decoded into, asserting LBCS0# when address offset is 00-
0Fh and LBCS1# when offset is 10-1Fh.
The region can be allocated to a single chip-select region
by assigning an address bit beyond the selected range to
Lower-Address-CS-Decode (but not above A8). In the
DS-0020 Jun 05
OXmPCI952
above example, if the user selects A5 as the Lower-
Address-CS-Decode, A[6:5] will be used to internally
decode chip-selects. As in this example LBA[7:5] are
always zero, only the chip select line LBCS0# may be
selected. In this case address offset 00-1Fh asserts
LBCS0# and the other chip-select lines remain inactive
permanently.
Memory Space:
The memory base address registers have an allocated
fixed size of 4K bytes in the address space. Since the
Local Bus has 8 address lines and the OXmPCI952 only
implements DWORD aligned accesses in memory space,
the 256 bytes of addressable space per chip select is
expanded to 1K. Unlike an I/O access, for a memory
access the upper address lines are always active and the
internal chip-select decoding logic ignores the user setting
for Lower-Address-CS-Decode (LT2[26:23]) and uses PCI
AD[11:10] to decode into 4 chip-select regions. When the
Local Bus is accessed in memory space, A[9:2] are
asserted on LBA[7:0]. The chip-select regions are defined
below.
Local Bus
Chip-Select
(Data-Strobe)
LBCS0# (LBDS0#)
LBCS1# (LBDS1#)
LBCS2# (LBDS2#)
LBCS3# (LBDS3#)
PCI Offset from BAR 1 in
Function1 (Memory space)
Lower Address Upper Limit
000h
3FCh
400h
7FCh
800h
BFCh
C00h
FFCh
Table 4: PCI address map for local bus (memory)
Note: The description given for I/O and memory accesses is for an Intel-
type configuration for the Local Bus. For Motorola-type configuration, the
chip select pins are redefined as data strobe pins. In this mode the Local
Bus offers up to 8 address lines and four data-strobe pins.
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