OXMPCI952 Datasheet, PDF (101/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Read from EPP Address Register (EPP Read Address cycle)
PCI CLK no (1^st Transaction)
1
- Start of PCI Read from EPP Address register
4
- Start of EPP address read cycle on parallel port side.
8
- PCI transaction completes with a ‘retry’ (without affecting current EPP read address cycle) as EPP cycle cannot complete within 16 PCI CLK cycles
8-9
- Peripheral Asserts BUSY in response to the host driving SLIN_N low.
12
- Host responds to BUSY by de-asserting SLIN_N (3 clock cycles after sampling BUSY)
15-16 - Peripheral Deasserts BUSY
- EPP cycle completed.
PCI CLK no (Retry Transaction)
1
- Start of Retry transaction, to the original read from EPP address register
5
- Retry transaction completes with “Data Transfer”, without initiating another EPP read address cycle.
Tslin (PCI clk to valid SLIN_N) - 22ns max*
Tpd (PCI clk to valid Port Address) - 22ns max*
EPP Read Address Cycle duration is dependant upon the timing response of the peripheral’s BUSY line and the parallel port
filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the
host to the peripheral’s BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
DS-0020 Jun 05
Page 101