OXMPCI952 Datasheet, PDF (28/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
5.3.3 PCI access to parallel port
When the parallel port is enabled (mode = 1), access to the
Parallel Port works via BAR definitions as usual, except
that there are two I/O BARs corresponding to the two sets
of registers defined to operate an IEEE1284 EPP/ECP and
bi-directional Parallel Port.
The user can change the I/O space block size of BAR0 by
over-writing the default values in LT2[25:20] using the
serial EEPROM (see section 5.4). For example the user
can reduce the allocated space for BAR0 to 4 bytes by
setting LT2[22:20] to ‘001’. The I/O block size allocated to
BAR1 is fixed at 8 Bytes.
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
OXmPCI952
DS-0020 Jun 05
Page 28