OXMPCI952 Datasheet, PDF (20/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Parallel port
Mode 1
G12
Dir¹ Name
OD(h) STB#
K13,K14,K15,J12,J14,H12,
H15,H13
H14
O(h) WRITE#
I/O(h) PD[7:0]
O PDOUT
Description
Strobe (SPP mode). Used by peripheral to latch data
currently available on PD[7:0]
Write (EPP mode). Indicates a write cycle when low and a
read cycle when high
Parallel data bus
Parallel Port data out enable. This pin should be used by
external transceivers for 5V signalling; it is high when PD[7:0]
are in output mode and low when they are in input mode.
Multi-purpose & External interrupt pins
Dir¹
Mode 0
Mode 1
B11
-
I/O(h)
Name
MIO0
-
B11
O
NC
A11
A11
I/O(h) MIO1
A11
A11
0 NC
C11
C11
I/O(h) MIO2
C11
C11
L14,K12,L15,A13,C12,B12,
A12,D11
I PME_In
I/O(h) MIO[10:3]
EEPROM pins
Mode 0, Mode 1
R1
M4
P3
N2
Dir¹
O
O
IU(h)
Name
EE_CK
EE_CS
EE_DI
O EE_DO
Description
Multi-purpose I/O 0. Can drive high or low, or assert a PCI
interrupt
Output Driving ‘0’. Can be left as a No-connect.
Multi-purpose I/O 1. Can drive high or low, or assert a PCI
interrupt (as long as LCC[6:5] = “00”).
Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)
Can be left as a No-Connect.
Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high
or low, or assert a PCI interrupt.
Input power management event. When LCC[7] is set this
input pin can assert a function 1 PME#.
Multi-purpose I/O pins. Can drive high or low, or assert a PCI
interrupt
Description
EEPROM clock
EEPROM active-high Chip Select
EEPROM data in, with internal pull-up.
When the serial EEPROM is connected, this pin should be
pulled up using a 1-10k resistor. Pin to be connected to the
external EEPROM’s EE_DO pin
EEPROM data out.
Pin to be connected to the external EEPROM’s EE_DI pin.
DS-0020 Jun 05
Page 20