OXMPCI952 Datasheet, PDF (45/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
PME# Generation from D3 Cold
In the miniPCI mode, the OXmPCI952 supports PME#
generation from the D3 cold state. This is indicated by bit
15 of both functions’ PCI power management register PMC
(Power Management Capabilities) that indicates “PME#
can be asserted from D3cold”. For all PCI modes, the PMC
register makes no such indications and all Power
Management Status and PME# context will be lost
following a PCI Reset.
For PME# generation in the D3cold, the OXmPCI952 is
required to make use of auxiliary 3.3v power when the
main 3.3v power has been removed. See Chapter 5 of the
PCI Local Bus Power Management Interface Specification.
This changeover to/from the main/auxiliary power needs to
be handled by the external circuitry that supplies Vcc to the
OXmPCI952, in such a way as to not cause any supply
interruptions (dropouts) as far as the OXmPCI952 device is
concerned. Otherwise, this will result in the loss of the
OXmPCI952’s internal states. The circuits must be such
that there are no sneak-paths between the main 3.3v
power and the Auxiliary 3.3v power as these power planes
are to be isolated at all times (miniPCI cards cannot
connect 3.3v AUX to 3.3v main, or vice versa).
When the OXmPCI952 device has been set up to provide
wake-up events (PME#), then the OXmPCI952 device will
generate PME# events via the Z_RI lines for function 0 and
via the MIO_2 line for function 1 when the device is in the
D3 cold state (while auxiliary powered).
The OXmPCI952 in the miniPCI mode preserves PME#
context when the device is transitioned from the D3 cold to
the D0 (uninitialised) transition via the Hardware Reset
invoked by the PCI RST# line. PME# Context is also
preserved following the soft reset when restoring a function
from the D3hot state.
When preserving the PME# context, the OXmPCI952
maintains the status of the following registers
Status of the PME_En bit Bit 8 of the function’s
PMCSR register.
Status of the PME_Status bit Bit 15 of the function’s
PMCSR register.
As a result, this preserves the Status of the PME# line.
Preserving PME# Context has 2 issues that need to be
handled by the host. These are listed here for reference
purposes only.
1. Since the PCI reset does not affect the status of
the fields PME_En and PME_Status, there is a
possibility that when power is first supplied to the
OXmPCI952 device (in the miniPCI mode of
operation) that the state of the PME# line is
unknown (PME_status is unknown). The host
controller must be able to handle this condition
until these 2 fields have been intialised by writing
to them with the appropriate values. This has
been noted in Section 3.2.4 of the PCI Power
Management Specification , revision 1.1, that
states “system software is required to explicitly
initialize all PME# context, for all functions,
during initial operating system load.” when PME#
generation from D3cold is supported.
2. In the D3cold state, when the OXmPCI952
generates a ‘wake-up’ (PME#) event, then this
status (PME# wakeup) persists when the
OXmPCI952 is transitioned from the D3cold state
to the D0(uninitialised) via a PCI Reset. The host
controller must be able to handle this condition
until the PME_status and/or PME_En bits have
been wriiten to with the appropriate values to
disable the PME# wake-up request.
DS-0020 Jun 05
Page 45