OXMPCI952 Datasheet, PDF (36/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Since reading the LSR clears LSR[7], the device driver-software should either flush or empty the contents of the receiver FIFO,
otherwise the Good-Data status will no longer be valid.
The UART Receiver FIFO Level (URL), UART Transmitter FIFO Level (UTL), UART Interrupt Source register (UIS) and Global
Interrupt Status register (GIS) are allocated adjacent address offsets (10h to 1Ch) in the Base Address Register. The device
driver-software can read all of the above registers in single burst read operation. The location offset of the registers are such that
the FIFO levels are usually read before the status registers so that the status of the N characters indicated in the receiver FIFO
levels are valid.
5.4.8 Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C)
Bits Description
Read/Write
EEPROM _PCI
1:0 UART Interrupt Status. These bits reflect the internal interrupt states of
-
R
UART1 to UART0, respectively.¹
3:2 Reserved.
-
R
4
MIO0 Status (When device mode = 0). This bit reflects the state of the internal
-
R
MIO[0]. The internal MIO[0] reflects the non-inverted or inverted state of MIO0
pin.²
When device mode = 1, this reflects state of the Parallel Port Interrupt.
-
R
5
MIO1 Status (LCC[6:5]=‘00’). This bit reflects the state of the internal MIO[1].
R
The internal MIO[1] reflects the non-inverted or inverted state of MIO1 pin.²
Function 0 Power-down Interrupt (LCC[6:5] ≠‘00’). In this mode this is a
sticky bit. When set, it indicates a power-down request issued by Function 0
and would normally have asserted a PCI interrupt if bit 21 was set (see section
8.6). Reading this bit clears it.
14:6 MIO[10:2] Status. These bits reflect the state of the internal MIO[10:2]. The
-
R
internal MIO[10:2] reflect the non-inverted or inverted state of MIO[10:2] pins
respectively.²
15 Reserved.
-
R
17:16 UART Interrupt Mask. When set (1) these bits enable the two internal UARTs W
RW
to assert a PCI interrupt respectively. When cleared (=0) they prevent the
respective channel from asserting a PCI interrupt.³
19:16 Reserved
W
RW
20
MIO[0] Interrupt Mask (When device mode = 0). When set (=1) this bit
W
RW
enables MIO0 pin to assert a PCI interrupt. When cleared (=0) it prevents
MIO0 pin from asserting a PCI interrupt.²
Parallel Port Interrupt Mask (When device mode = 1). When set (=1) this bit
W
RW
enables the Parallel Port to assert a PCI interrupt. When cleared (=0) it
prevents the Parallel Port from asserting a PCI interrupt.
21
MIO[1] Interrupt Mask (LCC[6:5]=‘00’). When set (=1) this bit enables MIO1
W
RW
pin to assert a PCI interrupt. When cleared (=0) it prevents MIO1 pin from
asserting a PCI interrupt.²
Function 0 Power-down Interrupt Mask (LCC[6:5] ≠‘00’). When set (=1) this
W
RW
bit enables the power-down logic in Function0 to assert a PCI interrupt. When
cleared (=0) it prevents the power-down logic in Function 0 from asserting a
PCI interrupt.
Reset
0x0h
0x0h
X
0
X
0
XXXh
X
3h
3h
1
1
1
0
DS-0020 Jun 05
Page 36