OXMPCI952 Datasheet, PDF (78/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
9 SERIAL EEPROM
9.1 Specification
The OXmPCI952 device requires programming via a serial
electrically-erasable programmable read only memory
(EEPROM) before the OXmPCI952 can be used. See
section 10.1.7 ”Minimum Programming Requirements” for
further details.
The EEPROM interface on the OXmPCI952 is based on
the proprietary serial interface known as Microwire^TM. The
interface has four pins which supply the memory device
with a clock, a chip-select and serial data input and output
lines. In order to read from such a device, a controller has
to output serially a read command and an address, and
then input serially the data.
The EEPROM interface auto-detects a variety of Microwire
compatible EEPROM devices attached to its interface,
where the data has been organised as a 16-bit data word
format. Devices supported include the NM93C46, C56,
C66, C76, and C86.
The OXmPCI952 reads data from the serial EEPROM and
writes data into the configuration register space
immediately after a PCI bus reset. This sequence ends
either when the controller finds no EEPROM is present or
when it reaches the end of the EEPROM data.
Following device configuration, driver software can access
the serial EEPROM through four bits in the device-specific
Local Configuration Register LCC[27:24]. Software can use
this register to manipulate the device pins in order to read
and modify the EEPROM contents.
In order to prevent an incorrectly coded EEPROM from
‘hanging’ the PCI system (since all PCI accesses will be
met with a retry while the external EEPROM device is
being accessed), the OXmPCI952 device incorporates an
EEPROM overrun detection mechanism that terminates the
EEPROM download if any attempts are made to read
beyond the size of the detect EEPROM. In this case, the
overrun flag is set in the local registers (LCC reg, bit 30).
The overrun condition does not reset the device to
eliminate the effects of any downloaded (corrupt) values so
any overrun indications must be handled by
reprogramming the device with the correct eeprom data, as
the state of the OXmPCI952 may be unknown.
A Windows® based utility is available to help generate
correct data for the EEPROM. For further details please
contact Oxford Semiconductor (see back cover).
DS-0020 Jun 05
Microwire^TM is a trade mark of National Semiconductor. For
a description of MicrowireTM, please refer to National
Semiconductor data manuals.
EEPROM Data Organisation
The serial EEPROM data is divided into six zones. The size
of each zone is an exact multiple of 16-bit WORDs. Zone0
is allocated to the header. A valid EEPROM program must
contain a header.
The EEPROM can be programmed from the PCI bus. Once
the programming is complete, the device driver should
either reset the PCI bus or set LCC[29] to reload the
OXmPCI952 registers from the serial EEPROM.
The general EEPROM data structure is shown in
EEPROM Zones
DATA
Zone
0
1
2
3
4
5
Size (Words)
One
One or more
One to four
Two or more
One or more
Two or more
Description
Header
Local Configuration Registers
Identification Registers
PCI Configuration Registers
Power Management Data
Function Access
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