OXMPCI952 Datasheet, PDF(34/108 Page) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

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OXMPCI952 Datasheet, PDF (34/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

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OXFORD SEMICONDUCTOR LTD.

OXmPCI952

Bits

26:23

28:27

Description

Local Bus Chipâselect Parameter âLower-Address-CS-Decodeâ. 2

IO space in 8-bit Local Bus

0000 = A2

1000 = Res

0001 = A3

1001 = Res

0010 = A4

1010 = Res

0011 = A5

1011 = Res

0100 = A6

1100 = Res

0101 = A7

1101 = Res

0110 = A8

1110 = Res

0111 = A9

1111 = Res

Reserved

Local Bus Software Reset. When this bit is a 1 the Local Bus reset pin

is activated. When this bit is a 0 the Local Bus reset pin is de-activated. 3

Local Bus Clock Enable. When this bit is a 1 the Local Bus clock

(LBCK) pin is enabled. When this bit is a 0 LBCK pin is permanently low.

The Local Bus Clock is a buffered PCI clock.

Bus Interface Type. When low (=0) the Local Bus is configured to Intel-

type operation, otherwise it is configured to Motorola-type operation.

Note that when Mode[1:0] is â01â, this bit is hard wired to 0.

Read/Write

EEPROM PCI

Reset

â0001â

(=â0010â

for parallel

port)

Note 1:

Note 2:

Note 3:

Only values in the range of 0 to Ah (0-10 decimal) are valid. Other values are reserved as writing higher values causes the PCI interface to retry all

accesses to the Local Bus as it is unable to complete the transaction in 16 PCI clock cycles.

The Lower-Address-CS-Decode parameter is described in sections 5.3.2 & Section 10. These bits are unused for Memory access to the 8-bit Local

Bus which uses a fixed decoding to allocate 1K regions to 4 chip selects. For further information on the Local bus, see section 7.

Local Bus, UARTs and the Parallel Port are all reset with PCI reset. In Addition, the user can issue the Software Reset Command.

LT2[15:0] enable the card designer to control the data bus

during the idle periods. The default values will configure the

Local Bus data pins to remain forcing (LT2[7:4] = Fh).

LT[15:8] is programmed to place the bus in high-

impedance at the beginning of a read cycle and set it back

to forcing at the end of the read cycle. For systems that

require the data bus to stay in high-impedance, the card

designer should write an appropriate value in the range of

0h to Ah to LT2[7:4]. This will place the data bus in high

impedance at the end of the write cycle. Whenever the

value programmed in LT2[7:4] does not equal Fh, the Local

Bus controller will ignore the setting of LT2[15:8] as the

data bus will be high-impedance outside write cycles. In

this case the card designer should place external pull-ups

on the data bus pins LBD[7:0].

While the configuration data is read from the external

EEPROM, the LBD pins remain in the high-impedance

state.

The timing registers define the Local Bus timing

parameters based on signal changes relative to a

reference cycle which is defined as two PCI clock cycles

after IRDY# is asserted for the first time in a frame. The

following parameters are fixed relative to the reference

cycle.

The Local Bus address pins LBA[7:0] are asserted during

the reference cycle. In a write operation, the Local Bus

data is available during the reference cycle, however I/O

buffers change direction as programmed in LT2[3:0].

In a Motorola type bus write operation, the Read-not-Write

pin (LBRDWR#) is asserted (low) during the reference

cycle. In a read cycle this pin remains high throughout the

duration of the operation.

The default settings in LT1 & LT2 registers provide one PCI

clock cycle for address and chip-select to control signal

set-up time, one clock cycle for address and chip-select

from control signal hold time, two clock cycles of pulse

duration for read and write control signals and one clock

cycle for data bus hold time. These parameters are

acceptable for using external OX16C950, OX16C952 and

OX16C954 devices connected to the Local Bus, in Intel

mode. Some redefinition will be required if the bus is to be

operated in Motorola mode.

The user should take great care when programming the

Local Bus timing parameters. For example defining a value

for chip-select assertion which is larger that the value

defined for chip-select de-assertion or defining a chip-

select assertion value which is greater than control signal

assertion will result in obvious invalid local Bus cycles.

DS-0020 Jun 05

Page 34

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