OXMPCI952 Datasheet, PDF (39/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
5.6 Power Management
The OXmPCI952 is compliant with PCI Power
Management Specification Revision 1.1. This is indicated
by both functions by their Power Management Capabilities
Register (PMC).
Each logical function implements its own set of Power
Management registers and supports the power states D0,
D2 and D3. In miniPCI modes, PME# generation from
D3cold is also indicated which preserves PME# context
through the use of 3.3v Auxiliary power. See section 6.7
“miniPCI Support” for further details.
Power management is accomplished by handling the
power-down and power-up (“power management event”)
requests, that are asserted on the relevant function’s
interrupt pin and the PME# pin respectively. Each function
can assert the PME# pin independently.
Power-down requests are not defined by any of the PCI
Power Management specifications. It is a device-specific
feature and requires a bespoke device driver
implementation. The device driver can either implement the
power-down itself or use the special interrupt and power-
down features offered by the device to determine when the
function or device is ready for power-down.
It is worth noting that the PME# pin can, in certain cases,
activate the PME# signal when all power is removed from
the device. This will cause the PC to wake up from Low-
power state D3(cold). To ensure full cross-compatibility
with system board implementations, the use of an isolator
FET is recommended (See Diagram). If Power
Management capabilities are not required, the PME# pin
can be treated as no-connect.
S
D
PCI connector
PME#
PME#
G
VDD
PME# Isolator Circuitry
DS-0020 Jun 05
OXmPCI952
5.6.1 Power Management of Function 0
Provided that the necessary controls have been set in the
device’s local configuration registers (LCC and GIS), the
two internal UARTs can be programmed to issue
powerdown requests and/or ‘wakeup’ requests (power
management events), for function 0.
Function 0 can be configured to monitor the activity of the 2
serial channels, and issue a power-down interrupt when
both of the UARTs are inactive (no interrupts pending and
both transmitters and receivers are idle).
When both the serial channels are indicating a powerdown
request only then will the internal power management
circuitry wait for a period of time as programmed into the
Power-Down Filter Time. This time is defined by the local
configuration register, LCC[7:5]). If the powerdown
requests remain valid for this time (this means that both
serial channels are still inactive) then the OXmPCI952 will
issue a powerdown interrupt on this function’s interrupt pin,
if this option is enabled. Alternatively, the device driver can
poll function 0’s powerdown status field in the local
configuration register GIS[5] to determine a powerdown
request. The powerdown filter stops the UARTs from
issuing too many powerdown interrupts whenever the
UARTs activity is intermittent.
Upon a power down interrupt, the device driver can change
the power-state of the device (function 0) as required. Note
that the power-state of function 0 is only changed by the
device driver and at no point will the OXmPCI952 change
its own power state. The powerdown interrupt merely
informs the device driver that this logical function is ready
for power down. Before placing the device into the lower
power states, the driver must provide the means for the
function to generate a ‘wakeup’ (power management)
event.
Whenever the device driver changes function 0’s power-
state to state D2 or D3, the device takes the following
actions:
• The internal clock to the internal UARTs is shut down.
• PCI interrupts are disabled regardless of the values
contained in the GIS registers.
• Access to I/O or Memory BARs is disabled.
However, access to the configuration space is still enabled.
The device driver can optionally assert/de-assert any of its
selected (design dependent) MIO pins to switch-off VCC,
disable other external clocks, or activate shut-down modes.
The device can only issue a wakeup request (a power
management event, PME#) if it is enabled by this function’s
PME_En bit, bit-8 of the PCI Power Management Register
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