OXMPCI952 Datasheet, PDF (35/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
5.4.5 UART Receiver FIFO Levels ‘URL’ (Offset 0x10)
The receiver FIFO level of the two internal UARTs are shadowed in Local configuration registers as follows:
Bits
7:0
15:8
31:16
Description
UART0 Receiver FIFO Level (RFL[7:0])
UART1 Receiver FIFO Level (RFL[7:0])
Reserved
Read/Write
EEPROM
PCI
-
R
-
R
-
R
Reset
0x00h
0x00h
0x0000h
5.4.6 UART Transmitter FIFO Levels ‘UTL’ (Offset 0x14)
The transmitter FIFO level of the two UARTs are shadowed in Local configuration registers as follows:
Bits
7:0
15:8
31:16
Description
UART0 Transmitter FIFO Level (TFL[7:0])
UART1 Transmitter FIFO Level (TFL[7:0])
Reserved
Read/Write
EEPROM
PCI
-
R
-
R
-
R
Reset
0x00h
0x00h
0x0000h
5.4.7 UART Interrupt Source Register ‘UIS’ (Offset 0x18)
The UART Interrupt Source register is described below:
Bits
5:0
11:6
26:12
27
28
30:29
31
Description
Read/Write
EEPROM
PCI
UART0 Interrupt Source Register (ISR[5:0])
-
R
UART1 Interrupt Source Register (ISR[5:0])
-
R
Reserved
-
R
UART0 Good-Data Status
-
R
UART1 Good-Data Status
-
R
Reserved
-
R
Global Good-Data Status. This bit is the logical AND of bits 27 to 28,
-
R
i.e. it is set if Good-Data Status of all internal UARTs is set.
Reset
01h
01h
XXXh
1
1
3h
1
Good-Data status for a given internal UART is set when all of the following conditions are met:
• ISR reads a level0 (no-interrupt pending), a level 2a (receiver data available, a level 2b (receiver time-out) or a level 3
(transmitter THR empty) interrupt
• LSR[7] is clear so there is no parity error, framing error or break in the FIFO
• LSR[1] is clear so no over-run error has occurred
If the device driver software reads the receiver FIFO levels (URL) followed by this register, then if Good-Data status for a given
channel is set, the driver can remove the number of bytes indicated by the FIFO level without the need to read the line status
register for that channel. This feature enhances the driver efficiency.
For a given channel, if the Good-Data status bit is not set, then the software driver should examine the corresponding ISR bits.
For example if bit 28 is low, then the driver should examine bits 11 down to 6 to obtain the ISR[5:0] for UART1. If the ISR
indicates a level 4 or higher interrupt, the interrupt is due to a change in the state of modem lines or detection of flow control
characters. The device driver-software should then take appropriate measures as would in any other 550/950 driver. When ISR
indicates a level 1 (receiver status) interrupt then the driver can examine the Line Status Register (LSR) of the relevant channel.
DS-0020 Jun 05
Page 35