OXMPCI952 Datasheet, PDF (87/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Symbol
tref
tza
tawr
tzwcs1
tzwcs2
tcswr
twrcs
tzwr1
tzwr2
tzdv
tzdf
twrdi
Parameter
IRDY# falling to reference LBCLK
Reference LBCLK to Address Valid
Address Valid to LBWR# falling
Reference LBCLK to LBCS# falling
Reference LBCLK to LBCS# rising
LBCS# falling to LBWR# falling
LBWR# rising to LBCS# rising
Reference LBCLK to LBWR# falling
Reference LBCLK to LBWR# rising
Reference LBCLK to data bus valid
Reference LBCLK to data bus high-impedance
LBWR# rising to data bus invalid
Min
Max
Nominally 2 PCI clock cycles
4.2
13.2
2.4
8.0
3.2
11.0
2 PCI clks + 6.6 2 PCI clks + 21.6
3.2
10.2
3.0
10.2
6.6
30.0
2 PCI clks + 3.6 2 PCI clks + 11.6
4.0
12.8
Note1
Note1
Note1
Note1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 28: Write operation to Intel-type Local Bus
Symbol
tref
tza
tads
tzrds1
tzrds2
vtdrd
tzd1
tzd2
tsd
thd
Parameter
IRDY# falling to reference LBCLK
Reference LBCLK to Address Valid
Address Valid to LBDS# falling
Reference LBCLK to LBDS# falling
Reference LBCLK to LBDS# rising
Data bus floating to LBDS# falling
Reference LBCLK to data bus floating at the start of the
read transaction
Reference LBCLK to data bus driven by OXmPCI952 at the
end of the read transaction
Data bus valid to LBDS# rising
Data bus valid after LBDS# rising
Min
Max
Nominally 2 PCI clock cycles
3.8
12.0
2.4
8.8
6.4
20.6
3 PCI clks + 3.6 3 PCI clks + 11.8
2.2
7.4
4.0
13.4
4 PCI clks + 3.8 4 PCI clks + 13.0
10.8
-
0
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 29: Read operation from Motorola-type Local Bus
Symbol
tref
tza
tads
tzw1
tzw2
twds
tdsw
tzwds1
tzwds2
tzdv
tzdf
tdsdi
Parameter
IRDY# falling to reference LBCLK
Reference LBCLK to Address Valid
Address Valid to LBDS# falling
Reference LBCLK to LBRDWR# falling
Reference LBCLK to LBRDWR# rising
LBRDWR# falling to LBDS# falling
LBDS# rising to LBRDWR# rising
Reference LBCLK to LBDS# falling
Reference LBCLK to LBDS# rising
Reference LBCLK to data bus valid
Reference LBCLK to data bus high-impedance
LBDS# rising to data bus invalid
Min
Max
Nominally 2 PCI clock cycles
4.2
13.2
2.2
7.6
3.6
11.6
2 PCI clks + 6.6 2 PCI clks + 21.2
2.6
9.2
3.0
9.6
6.4
20.8
2 PCI clks + 3.6 2 PCI clks + 12.0
4.0
13.0
Note1
Note1
Note1
Note1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 30: Write operation to Motorola-type Local Bus
Note1 : For local bus writes, values on the data bus persist until the next read/write local bus transaction.
DS-0020 Jun 05
Page 87