OXMPCI952 Datasheet, PDF (4/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
6.6 INTERRUPTS & SLEEP MODE........................................................................................................................................ 57
6.6.1 INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 57
6.6.2 INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 58
6.6.3 INTERRUPT DESCRIPTION ........................................................................................................................................ 58
6.6.4 SLEEP MODE ............................................................................................................................................................... 59
6.7 MODEM INTERFACE ....................................................................................................................................................... 59
6.7.1 MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 59
6.7.2 MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 60
6.8 OTHER STANDARD REGISTERS ................................................................................................................................... 60
6.8.1 DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 60
6.8.2 SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 60
6.9 AUTOMATIC FLOW CONTROL....................................................................................................................................... 61
6.9.1 ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 61
6.9.2 SPECIAL CHARACTER DETECTION .......................................................................................................................... 62
6.9.3 AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 62
6.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 62
6.10 BAUD RATE GENERATION............................................................................................................................................. 63
6.10.1 GENERAL OPERATION ............................................................................................................................................... 63
6.10.2 CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 63
6.10.3 TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 63
6.10.4 EXTERNAL 1X CLOCK MODE..................................................................................................................................... 65
6.10.5 CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 65
6.11 ADDITIONAL FEATURES ................................................................................................................................................ 65
6.11.1 ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 65
6.11.2 FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 66
6.11.3 ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 66
6.11.4 TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 67
6.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 67
6.11.6 FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’ .................................................................................................................... 67
6.11.7 DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 67
6.11.8 CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 68
6.11.9 NINE-BIT MODE REGISTER ‘NMR’ ............................................................................................................................. 68
6.11.10 MODEM DISABLE MASK ‘MDM’ .................................................................................................................................. 69
6.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 69
6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 69
6.11.13 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 69
6.11.14 CLOCK ALTERATION REGISTER ‘CKA’ ..................................................................................................................... 70
7 LOCAL BUS ........................................................................................................................................ 71
7.1 OVERVIEW ....................................................................................................................................................................... 71
7.2 OPERATION ..................................................................................................................................................................... 71
7.3 CONFIGURATION & PROGRAMMING............................................................................................................................ 72
8 BIDIRECTIONAL PARALLEL PORT .................................................................................................. 73
8.1 OPERATION AND MODE SELECTION ........................................................................................................................... 73
8.1.1 SPP MODE ................................................................................................................................................................... 73
8.1.2 PS2 MODE.................................................................................................................................................................... 73
8.1.3 EPP MODE ................................................................................................................................................................... 73
8.1.4 ECP MODE ................................................................................................................................................................... 73
8.2 PARALLEL PORT INTERRUPT ....................................................................................................................................... 74
8.3 REGISTER DESCRIPTION............................................................................................................................................... 75
8.3.1 PARALLEL PORT DATA REGISTER ‘PDR’ ................................................................................................................. 75
8.3.2 ECP FIFO ADDRESS / RLE ......................................................................................................................................... 75
8.3.3 DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 75
8.3.4 DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 76
8.3.5 EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 76
8.3.6 EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 76
DS-0020 Jun 05
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