OXMPCI952 Datasheet, PDF (103/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
PCI CLK no (Parallel Port already placed in the reverse ECP transfer mode)
2
- Start of 1^st ECP reverse transfer by peripheral
2-3
- Peripheral asserts ACK_N low
6
- Host responds by asserting AFD_N (3 clock cycles after sampling ACK_N low)
10-11 - Peripheral deasserts ACK_N
13
- Host responds by de-asserting AFD_N (2 clock cycles after sampling ACK_N low)
- End of ECP reverse transfer (data already transferred to ECP DFIFO)
24
- Start of PCI read from ECP DFIFO (does not initiate or affect any ECP reverse transfers that may be taking place)
26
- Start of 2nd ECP reverse transfer by peripheral.
Tafd (PCI clk to AFD_N valid) : 22ns max*
Tack-afd : 3 clock cycles (see below) + Tafd
ECP Reverse Transfer Cycle duration is dependant upon the timing response of the peripheral’s ACK_N line and the parallel
port filters.Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of
the host to the peripheral’s ACK_N line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
DS-0020 Jun 05
Page 103