OXMPCI952 Datasheet, PDF (100/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Write to EPP Address Register (EPP Write Address cycle)
PCI CLK no (1^st Transaction)
1
- Start of PCI write to EPP Address register
5
- Start of EPP address write cycle on parallel port side.
8
- PCI transaction completes with a ‘retry’ (without affecting current EPP write address cycle) as EPP cycle cannot complete within 16 PCI CLK cycles
7-8
- Peripheral Asserts BUSY
11
- Host responds to BUSY by de-asserting SLIN_N (4 clock cycles after sampling BUSY)
14-15 - Peripheral Deasserts BUSY
17
- Host responds to BUSY by asserting SLIN_N and the parallel port data lines (2 clock cycles after sampling BUSY).
- EPP cycle completed.
PCI CLK no (Retry Transaction)
1
- Start of Retry transaction, to the original write to EPP address register
5
- Retry transaction completes with “Data Transfer”, without initiating another EPP write address cycle.
Tslin (PCI clk to valid SLIN_N) - 22ns max*
Tstb (PCI clk to valid STB_N)
- 22ns max*
Tpd (PCI clk to valid port Address) - 22ns max*
EPP Write Address Cycle duration is dependant upon the timing response of the peripheral’s BUSY line and the parallel port
filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the
host to the peripheral’s BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
DS-0020 Jun 05
Page 100