OXMPCI952 Datasheet, PDF (40/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
PMCSR. PME# assertion, is immediate and does not use
the powerdown filter timer. It operates even if the
powerdown filter time is set to disabled.
Like powerdown, wakeup requests for function 0 can be
generated by each serial channel. The means to generate
wakeup events from these sources will have been set up
prior to placing this function into the powerdown states D2
or D3 (including setting of the PME_En bit).
For each of the two UARTs, when the device (function 0) is
in the powerstate D3, only activity on the serial channel’s
RI# line (the trailing edge of a pulse) will generate a
wakeup event. When the device (function 0) is in the
power-state D2, then wake-ups are configurable. In this
case, a change in the state of any modem line (which is
enabled by a 16C950-specific mask bit) or a change in the
state of the serial input line (again, if enabled by a 16C950-
specific mask bit) can issue a wake up request on the
PME# pin. It is worth noting that after a hardware reset all
of these mask bits are cleared to enable wake up assertion
from all modem lines and the SIN line when in the
powerstate D2. As the wake up operation from D2 requires
at least one mask bit to be enabled, the device driver can
for example disable the masks with the exception of the
Ring Indicator, so only a modem ring can wake up the
computer. In the case for a wake up request from the serial
input line EXT_DATA_IN (from the power state D2) then
the clock for that channel is turned on so serial data
framing can be maintained.
When function 0 issues a wake up request from the serial
channels, the PME_Status bit in this function’s PCI power
management registers (PMCSR[15]) will be set. This is a
sticky bit which will only be cleared by writing a ‘1’ to it.
While PME_En (PMCSR[8]) remains set, the PME_Status
will continue to assert the PME# pin to inform the device
driver that a power management wake up event has
occurred. After a wake up event is signalled, the device
driver is expected to return this function to the D0 power-
state.
5.6.2 Power Management of function 1
Provided that the necessary controls have been set in the
device’s local configuration registers (MIC and GIS), up to
8 Multi_Purpose pins (MIO[10:3]) can be programmed to
issue powerdown requests but only MIO[2] can be set to
generate ‘wakeup’ requests (power management events),
for function 1. The Parallel Port or the Local Bus function
are not capable of issuing powerdown requests or power
management events but can be placed in a low power
state through power management involving the MIO pins.
DS-0020 Jun 05
OXmPCI952
The state of the MIO pin(s) that issues a powerdown
request is controlled by the MIC register. This can be active
high or active Low. This state can be the same MIO state
that asserts function 1’s interrupt pin for normal
functionality. The assertion of the MIO pins will result in a
function 1 powerdown request being made immediately.
There is no powerdown filtering time associated with
function 1.
The powerdown request can be issued on the function’s
interrupt pin, if this option is enabled.
Upon a power down interrupt, the device driver can change
the power-state of the device (function 1) as required. Note
that the power-state of function 1 is only changed by the
device driver and at no point will the OXmPCI952 change
its own power state. The powerdown interrupt merely
informs the device driver that this logical function is ready
for power down. Before placing the device into the lower
power states, the driver must provide the means for the
function to generate a ‘wakeup’ (power management)
event.
Whenever the device driver changes function 1’s power-
state to state D2 or D3, the device takes the following
actions:
• Parallel Port placed in a low power mode.
• Local Bus Function placed in a low power mode
• PCI interrupts are disabled regardless of the values
contained in the GIS registers.
• Access to I/O or Memory BARs is disabled.
However, access to the configuration space is still enabled.
Function 1 can only issue a wakeup request (power
management event) if it is enabled by this function’s
PME_En bit, bit-8 of the PCI Power Management Register
PMCSR.
Wakeup requests for function 1 can only be generated by
the Multi_Purpose I/O pin MIO[2]. The means to generate
wakeup events from this source will have been set up prior
to placing this function into the powerdown states D2 or
D3.
The state of the MIO[2] pin that results in wakeup requests
is determined by the settings in the local configuration
register MIC. As soon as the correct logic is invoked than a
power management event (wakeup) is asserted. The
PME# event is immediate.
When function 1 issues a wake up request, the
PME_Status bit in this function’s PCI power management
registers (PMCSR[15]) will be set. This is a sticky bit which
will only be cleared by writing a ‘1’ to it. While PME_En
(PMCSR[8]) remains set, the PME_Status will continue to
assert the PME# pin to inform the device driver that a
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