OXMPCI952 Datasheet, PDF (3/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
TABLE OF CONTENTS
1 BLOCK DIAGRAM ................................................................................................................................ 8
2 PIN INFORMATION—160-PIN LQFP .................................................................................................... 9
2.1 PINOUTS............................................................................................................................................................................. 9
2.2 PIN DESCRIPTIONS......................................................................................................................................................... 10
3 PIN INFORMATION—176-PIN BGA.................................................................................................... 16
3.1 PINOUTS........................................................................................................................................................................... 16
3.2 PIN DESCRIPTIONS......................................................................................................................................................... 17
4 CONFIGURATION & OPERATION ..................................................................................................... 22
5 PCI TARGET CONTROLLER.............................................................................................................. 23
5.1 OPERATION ..................................................................................................................................................................... 23
5.2 CONFIGURATION SPACE ............................................................................................................................................... 23
5.2.1 PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 24
5.3 ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 26
5.3.1 PCI ACCESS TO INTERNAL UARTS........................................................................................................................... 26
5.3.2 PCI ACCESS TO 8-BIT LOCAL BUS............................................................................................................................ 27
5.3.3 PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 28
5.4 ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 29
5.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 29
5.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 30
5.4.3 LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 32
5.4.4 LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): ................................................................. 33
5.4.5 UART RECEIVER FIFO LEVELS ‘URL’ (OFFSET 0X10)............................................................................................. 35
5.4.6 UART TRANSMITTER FIFO LEVELS ‘UTL’ (OFFSET 0X14)...................................................................................... 35
5.4.7 UART INTERRUPT SOURCE REGISTER ‘UIS’ (OFFSET 0X18)............................................................................... 35
5.4.8 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ................................................ 36
5.5 PCI INTERRUPTS............................................................................................................................................................. 38
5.6 POWER MANAGEMENT .................................................................................................................................................. 39
5.6.1 POWER MANAGEMENT OF FUNCTION 0 ................................................................................................................. 39
5.6.2 POWER MANAGEMENT OF FUNCTION 1 ................................................................................................................. 40
5.7 MINIPCI SUPPORT........................................................................................................................................................... 42
5.8 DEVICE DRIVERS ............................................................................................................................................................ 46
6 INTERNAL OX16C950 UARTS ........................................................................................................... 47
6.1 OPERATION – MODE SELECTION ................................................................................................................................. 47
6.1.1 450 MODE..................................................................................................................................................................... 47
6.1.2 550 MODE..................................................................................................................................................................... 47
6.1.3 EXTENDED 550 MODE ................................................................................................................................................ 47
6.1.4 750 MODE..................................................................................................................................................................... 47
6.1.5 650 MODE..................................................................................................................................................................... 47
6.1.6 950 MODE..................................................................................................................................................................... 48
6.2 REGISTER DESCRIPTION TABLES ............................................................................................................................... 49
6.3 RESET CONFIGURATION ............................................................................................................................................... 53
6.3.1 HARDWARE RESET .................................................................................................................................................... 53
6.3.2 SOFTWARE RESET ..................................................................................................................................................... 53
6.4 TRANSMITTER AND RECEIVER FIFOS ......................................................................................................................... 54
6.4.1 FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 54
6.5 LINE CONTROL & STATUS............................................................................................................................................. 55
6.5.1 FALSE START BIT DETECTION.................................................................................................................................. 55
6.5.2 LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 55
6.5.3 LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 56
DS-0020 Jun 05
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