OXMPCI952 Datasheet, PDF (38/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
5.5 PCI Interrupts
Interrupts in PCI systems are level-sensitive and can be
shared. There are up to thirteen sources of interrupt in the
OXmPCI952, one via each UART channel and up to eleven
from the Multi-Purpose IO pins (MIO10 to MIO0). The
Parallel Port and MIO[0] pin share the same interrupt
status bit (GIS[4]). The PCI Power Management power-
down interrupt for the internal UARTs (Function0) and the
MIO[1] pin share the status bit GIS[5]. The Local Bus uses
the MIO pins to pass interrupts to the PCI controller.
Function 0 and Function 1 interrupts are set to assert
on the INTA# line, by default. These default routings may
be modified by writing to the Interrupt Pin field in the
configuration registers using the serial EEPROM facility.
The Interrupt Pin field is normally considered a hard-wired
read-only value in PCI. It indicates to system software
which PCI interrupt pin (if any) is used by a function. The
interrupt pin may only be modified using the serial
EEPROM facility, and card developers must not invoke any
combination which violates the PCI specification. If in
doubt, the default routings should be used. The Following
Table relates the Interrupt Pin field to the device pin used.
Interrupt Pin
0
1
2
3 to 255
Device Pin used
None
INTA#
INTB#
Reserved
Note that the OXmPCI952 only has two PCI interrupt pins : INTA# and
INTB#. In the miniPCI mode, INTB# is not available as an interrupt line as
the pin is redefined as a dedicated CLKRUN# line.
During the system initialisation process and PCI device
configuration, system-specific software reads the interrupt
pin field to determine which (if any) interrupt pin is used by
each function. It programmes the system interrupt router to
logically connect this PCI interrupt pin to a system-specific
interrupt vector (IRQ). It then writes this routing information
to the Interrupt Line field in the function’s PCI configuration
space. Device driver software must then hook the interrupt
using the information in the Interrupt Line field.
Interrupt status for all thirteen sources of interrupt is
available using the GIS register in the Local Configuration
Register set, which can be accessed using I/O or Memory
accessed from both logical functions. This facility enables
each function to snoop on interrupts asserted from the
other function regardless of the interrupt routing.
The interrupt from each UART channel is enabled using
the IER register and the MCR register for that UART. If the
interrupt is enabled and active, then the device will drive
the PCI interrupt pin low. Generic device driver software
will use the IER register to enable interrupts. The
OXmPCI952 offers additional interrupt masking ability
using GIS[17:16] (see section 5.4.8). An internal UART
channel may assert a PCI interrupt if the interrupt is
enabled by IER and GIS[17:16].
All interrupts can be enabled / disabled individually using
the GIS register set in the Local configuration registers.
When an MIO pin is enabled, an external device can assert
a PCI interrupt by driving that pin. The sense of the MIO
external interrupt pins (active-high or active-low) is defined
in the MIC register. The parallel port can also assert an
interrupt (but this will effectively disable the MIO[0]
interrupt).
DS-0020 Jun 05
Page 38